1. Field of the Invention
The present invention relates generally to an improved data processing system, and in particular, to a computer implemented method for improving the performance of applications executing in a data processing system. Still more particularly, the present invention relates to a computer implemented method, system, and computer usable program code for improved register allocation for hardware-enabled threads in simultaneous multithreaded processors.
2. Description of the Related Art
An application executing in a data processing system spawns threads that are executed by a processor in the data processing system. A thread is a thread of execution resulting from a division of a computer program into two or more tasks. The implementation of threads and processes differs from one operating system to another, but in most cases, a thread is contained inside a process associated with the application. Multiple threads can exist within the same process and share resources such as memory.
During execution, a thread has to maintain state information. This state information is called architectural state and is usually stored in registers. A register is space to hold data, such as state of a thread. A register is usually designed and located such that storing data into and reading data from a register is fastest compared to similar operation with other memory locations in a given data processing system.
A physical register is a register constructed in hardware. A logical register is a data structure usable by an application, such as by a thread of an application, in a manner similar to using a register. A logical register is mapped to a physical register. Typically, for storing state information, a thread does not reference a physical register directly. A thread reads or writes the state information in a logical register, and the reading or writing is directed to the correct mapped physical register.
Simultaneous multi-threading (SMT) is a technology that allows multiple threads to execute on a processor unit concurrently. Each thread in SMT architectures still has to maintain its own state using registers. In a data processing system employing SMT technology, multiple threads can have physical registers allocated to them simultaneously for storing their respective state information.